1. Field of the Invention
This invention relates to electronic circuits, and more particularly to clock generation circuits such as phase locked loops and delay locked loops.
2. Description of the Related Art
Phase-locked loops (PLL's) and/or delay-locked loops (DLL's) are commonly used to provide clock signals in digital circuits. A typical PLL or DLL includes a phase detector and a voltage-controlled element (VCE). In a PLL, the voltage-controlled element is a voltage-controlled oscillator (VCO) that outputs a frequency that is proportional to a received input voltage. In a DLL, the voltage-controlled element is a voltage-controlled delay line (VCDL), which delays a clock signal in proportion to a received input voltage.
In digital integrated circuits, PLL's and DLL's may suffer from various noise sources, including input clock noise and power supply noise. These noise sources can produce an unwanted variation in the timing of signals commonly referred to as jitter. In larger, more complex digital systems, the effect of power supply noise on an output clock signal provided by a PLL/DLL may be significant.
Various techniques have been employed to minimize the effects of jitter resulting from power supply noise. One such technique is to implement the circuit (particularly the VCE of a PLL or DLL) using differential amplifiers with symmetric load architecture as a delay element in order to reject power supply noise that appears as common-mode noise. This technique may provide excellent noise rejection characteristics. However, the maximum operating speed may be limited for PLL's and DLL's implemented using this architecture. For digital integrated circuits with clock speeds in the gigahertz range, this architecture may be unsuitable.
Another technique that may be more suitable for high-speed digital integrated circuits is to provide an additional on-chip DC-DC voltage regulator to provide a clean power supply for the PLL/DLL. However, this technique is significantly more complex than using the differential architecture discussed above, and requires additional circuit area. The additional complexity includes the necessity to provide a bandgap circuit for providing a constant voltage reference. The bandgap reference requires parasitic bipolar devices implemented in a CMOS process. Thus, while this technique may be suitable for high-speed digital designs, it involves significant overhead in design complexity, and circuit area.